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Title
A Formal Verification Case Study for IEEE-P.896 Bus Arbiter by using A Model Checking Tool
Author
Katsumi Wasaki
Vol. 7 No. 3 pp. 184-192
Keywords
Formal Verification, Model Checking, Temporal Logic, Bus Arbiter, Hardware Description Languages
A Realization and Verification of A Parallel Image Processing Controller by using An Extended Petri net
Vol. 7 No. 3 pp. 258-263
Extended Petri nets, Flexible Manufacturing Systems, Image Processing Controllers, System Verification
A Realization of the Persistence of Petri Net State Spaces using XML Data Deployment
Vol. 8 No. 3 pp. 92-97
System Reliability, Petri Nets, State Space Persistency and XML
Self-Stabilizing Model of A Memory Controller based on the Cellular Automata
Vol. 8 No. 3 pp. 222-227
Cellular Automata, Self-Stabilizing, Fault Tolerant and Fault Masking