Title	Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA
Author	Muhammad H. Rais, Syed M. Qasim
Citation	Vol. 9  No. 9  pp. 59-63
Keywords	Advanced Encryption Standard (AES), FPGA, VHDL, Virtex-5

Title	A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box
Author	Muhammad H. Rais, Syed M. Qasim
Citation	Vol. 9  No. 9  pp. 305-309
Keywords	Advanced Encryption Standard (AES), Very High Speed Integrated Circuit Hardware Description Language (VHDL), Field Programmable Gate Array (FPGA), Virtex-5

Title	Efficient FPGA Realization of S-Box using Reduced Residue of Prime Numbers
Author	Muhammad H. Rais, Syed M. Qasim
Citation	Vol. 10  No. 1  pp. 69-74
Keywords	Advanced Encryption Standard (AES), S-Box, FPGA, VHDL, Virtex-5

Title	FPGA Design and Implementation of Matrix Multiplier Architectures for Image and Signal Processing Applications
Author	Syed M. Qasim, Ahmed A. Telba, Abdulhameed Y. AlMazroo
Citation	Vol. 10  No. 2  pp. 168-176
Keywords	FPGA, Matrix Multiplier, Systolic Array, VLSI