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Title |
Efficient FPGA Realization of S-Box using Reduced Residue of Prime Numbers |
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Author |
Muhammad H. Rais, Syed M. Qasim |
| Citation |
Vol. 10 No. 1 pp. 69-74 |
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Abstract |
A high performance substitution box (S-Box) implementation using reduced residue of prime numbers is presented in this paper. The byte substitution implemented using S-Box is an important part of the Advanced Encryption Standard (AES). The objective of this paper is to present an efficient Field Programmable Gate Array (FPGA) realization of S-Box using very high speed integrated circuit hardware description language (VHDL). The design was implemented on Xilinx Virtex-5 XC5VLX50 FPGA and the results obtained show that the proposed method provides an improved performance with 38% improvement in maximum clock frequency as well as efficient utilization of FPGA hardware resources. |
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Keywords |
Advanced Encryption Standard (AES), S-Box, FPGA, VHDL, Virtex-5 |
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