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Title
Using Dead Block Information to Minimize I-cache Leakage Energy
Author
Mohan G Kabadi, Ranjani Parthasarathi
Vol. 7 No. 5 pp. 95-105
Keywords
Power-efficient architecture, Low-leakage cache, Compiler-assisted energy optimization
An Asynchronous, Low Power and Secure Framework for Network-On-Chips
M. Mirza-Aghatabar, A. Sadeghi
Vol. 8 No. 7 pp. 214-223
Network-on-Chip, Router, Asynchronous, Low Power, Security
An Energy Sorting Protocol (ESP) With Low Energy and Low Latency in Wireless Sensor Networks
A.Allirani, M.Suganthi
Vol. 8 No. 11 pp. 208-214
Sensor networks, Low latency, Energy sorting protocol, data processing, Cluster formation
Correlated MIMO Rayleigh Channels: Eigenmodes and Capacity Analyses
A. Saad, M. Ismail, N. Misran
Vol. 8 No. 12 pp. 75-81
Channel correlation, Channel capacity, Channel eigenmodes, Low and high SNR