To search, Click below search items. |
| All Published Papers Search Service |
|
|
|
Title |
An Asynchronous, Low Power and Secure Framework for Network-On-Chips |
|
Author |
M. Mirza-Aghatabar, A. Sadeghi |
| Citation |
Vol. 8 No. 7 pp. 214-223 |
|
Abstract |
Network-on-Chip (NoC) is an approach to handle huge number of transistors by virtue of technology scaling to lower than 50nm. The issue of security has been always controversial to many designers. Among the attackers, one of the most important of them is power attacker which uses statistical techniques to determine the secret keys by observing power consumption. The power consumption spurs during runtime (1 to 0 and 0 to 1 switching) is based on charging and discharging of capacitors. In this paper we will introduce an asynchronous framework for NoC which is based on QDI, 4-Phase handshake signaling. We will show that our framework has lower power consumption compared to traditional synchronous router due to its asynchronous nature. We will also show that our framework is more secure against the power attackers due to its dual rail encoding style. We will synthesis our framework with Persia synthesis tool and will compare it with synchronous router from power consumption point of view under different traffic models, one and three number of virtual channels and AFBAR routing algorithm. |
|
Keywords |
Network-on-Chip, Router, Asynchronous, Low Power, Security |
|
URL |
