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Compute-Line based Computational Memory Architecture supporting Binary Logic with two Coloring States


Driss Azougagh, Ahmed Rebbani, and Omar Bouattane


Vol. 19  No. 6  pp. 60-67


Processing In Memory (PIM) is in demand more than ever to cope with the growth of Big Data, memory wall and power wall. It eliminates the overhead of data movement between processing unit and memory resulting in high bandwidth, massive parallelism, and high energy efficiency. Most existing PIM works are concentrated on near-memory processing (NMP) and/or in-memory processing (IMP). In this paper we present a compute-line based computational memory architecture (CCMA) supporting in compute-line processing, or simply compute-line, using a controlled inverter (CINV) for pull-down and/or pull-up the line. In one clock cycle, with one single and simple instruction, the compute-line allows multiple pull-downs and/or pull-ups for some bitwise logic computation and multiple writes, simultaneously. The architecture is easily backward compatible with conventional Static/Dynamic Random Access Memory (SRAM/DRAM) but it has advantage of not using bit-line pre-charging and sensing for read and write operations. It reduces bit-line activities by more than half. When used as an in-memory computing, it also eliminates overhead of data movement demonstrating a great potential to reduce bandwidth and energy consumption. The proposed compute-line is validated and tested to show considerable performance and effectiveness according to the new capabilities offered. This architecture can support a variety of interconnect topologies between multiple compute-lines which will benefit many parallel applications.


SRAM Memory, Built-in Computing, compute-line, in-place processing.