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Title |
Multi-Core Embedded Controller Security Architecture with Instruction Stream Detection |
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Author |
Xiaosheng Wang, Yanchun Yang |
| Citation |
Vol. 19 No. 5 pp. 147-155 |
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Abstract |
The paper presents a design scheme for multi-core embedded controller security architecture and a control application runtime unexpected behavior detection method based on instruction stream. In the architecture design, the partition and isolation functions of the hypervisor are used to consolidate the security- critical system and the non-security-critical system into a single hardware to be handled by different cores. The two cores cooperate with hardware-based instruction stream tracking module dynamically monitors whether the behavior of the control application executed by the monitored core deviates from the expectation to implement secure and reliable seamless control. The compatibility of different instruction sets and the impact of interrupt on detection are considered synthetically in the control application security detection algorithm. Finally, the effectiveness of the proposed method is verified by simulation experiments on ball and plate system. |
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Keywords |
Multi-core embedded controller, security Architecture, Hypervisor, Consolidating control unit, Instruction stream detection |
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