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Computational Memory Architecture Supporting in Bit-Line Processing


Driss Azougagh, Ahmed Rebbani, and Omar Bouattane


Vol. 18  No. 7  pp. 61-68


Processing In Memory (PIM) is in demand more than ever to cope with the growth of Big Data, memory wall and power wall. It eliminates the overhead of data movement between processing unit and memory resulting in high bandwidth, massive parallelism, and high energy efficiency. Most existing PIM works are concentrated on near-memory processing (NMP) and/or in-memory processing (IMP). In this paper we present a computational memory architecture supporting in bit-line processing, or simply compute-line, using Directed dual bit-line Keeper. In one clock cycle and through bit-line selection, the compute-line allow multi-rows read, bitwise logic compute and multi-rows write, simultaneously. The bit-line keeper projects the outcome in the selected bit-line to the non-selected one before write operation. The architecture is backward compatible with conventional Static Random Access Memory (SRAM) but it has advantage of not using bit-line pre-charging and sensing for read and write operations. It reduces bit-line activities by more than half. When used as an in-memory computing, it also eliminates overhead of data movement demonstrating considerable reduction in bandwidth and energy consumption. The proposed compute-line is validated and tested to show considerable performance and effectiveness according to the new capabilities offered. This architecture can support a variety of interconnect topology between multiple compute-lines which will benefit many parallel applications.


SRAM Memory, Built-in Computing, bit-line keeper, in-place processing.