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Design of embedded architecture for pedestrian detection in image and video


Taoufik Salem Saidani and Yahia Fahem Said


Vol. 17  No. 12  pp. 120-129


Today, pedestrian detection by real-time embedded systems remains a major challenge due to a number of factors. The task of detecting pedestrians in a road scene requires enormous time and resources. In this paper, a hardware architecture for pedestrian detection system is proposed. The system consists of a HOG descriptor extractor and an SVM classifier. The design is carried out using Xilinx's design tools: Vivado IPI, Vivado HLS and SDK for Hardware-Software Co-Design. The performance analysis of the implementation shows a significant acceleration in the classification process with a reduction of the energy consumption and logical resources required. As a result, with the tools chosen, the proposed architecture has the capability to support a real-time pedestrian detection system for HD video at 180 frames per second.


Pedestrian detection HOG-SVM Embedded architecture Zynq APSoC Real-time processing