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A High-Throughput FPGA Implementation of Quasi-Cyclic LDPC Decoder


Hossein Gharaee, Mahdie Kiaee, Naser Mohammadzadeh


Vol. 17  No. 3  pp. 140-149


Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Many important communication standards such as DVB-S2 and 802.16e use these codes. In this paper, an FPGA implementation of a partial-parallel QC-LDPC decoder is proposed based on the sum-product algorithm. We use a modified version of TPMP algorithm to improve the number of clock cycles, resource usage, and power consumption. The decoder is implemented for a code length of 672 with code rate of 3/4. Our implementation is achieved to maximum throughput of 3.3 Gbps with frequency of 280 MHz and its power consumption is less than 150mW.


QC-LDPC decoder, Time Scheduling, TPMP Algorithm, FPGA Implementation