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Title

Instructional Scaffolding for ASIP Design Education with System Verilog Assertion considering Situated Nature of Learning

Author

Ryuichi TAKAHASHI, Yoshiyasu TAKEFUJI

Citation

Vol. 16  No. 10  pp. 116-121

Abstract

This paper proposes a new method for bringing out challenges to study modern microprocessor design at the graduate course from an advanced senior project for application specific instruction set processor (ASIP) design using SystemVerilog assertion with related design verification technologies. We have already reported that the instruction issue logic for superscalar microprocessors works very well as an way-in of legitimate peripheral participation (LPP) to observe the system, since the instruction issue logic is tuned at the final stage of the design and is the central part of the system. The way-in gave opportunity for students to understand the mechanism of superscalar microprocessors. The fine grain microprocessor design education for junior students has been greatly improved. Our next step is to find more general solution to the subject to improve our microprocessor design education, since the instruction issue logic seemed to be too specialized for particular microprocessor design. The answer was SystemVerilog assertion (SVA) describing central part of the system with related model checking methodologies which are theoretical successor to the SVA. A senior student who designed a pipelined ASIP for Dijkstra’s algorithm as a senior student continued to study an extension of abstraction technique to investigate the behavior of the algorithm on the flowchart beside the Kripke structure for identifying the location of the bugs as a graduate study for his master’s thesis. Another senior student who designed another pipelined ASIP for Kruskal’s algorithm as a senior student continued to study derivation of sophisticated temporal logic equations from simple properties proved by simple model checking using inference rules with theories as his graduate study. We believe showing the central part of the system by using SVA with related technologies for the design verification will work very well for guiding the undergraduate students to learn the mechanism of the system as well as advanced studies of modern microprocessor design at the graduate course.

Keywords

ASIP, SVA, model checking, design verification, LPP

URL

http://paper.ijcsns.org/07_book/201610/20161018.pdf