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Performance study and synthesis of new Error Correcting Codes RS, BCH and LDPC Using the Bit Error Rate (BER) and Field-Programmable Gate Array (FPGA)


El habti El idrissi Anas, El gouri Rachid, Ahmed Lichioui, Hlou Laamari


Vol. 16  No. 5  pp. 21-28


Most communication networks involve physical phenomena of distortion and attenuation of the transmitted information and external disturbances associated with transport conditions or communication equipment. Therefore, this information is often corrupted in reception. The RS codes (Reed-Solomon), LDPC codes (Low-Density Parity-Check) and BCH codes (Bose, Ray-Chaudhuri and Hocquenghem) are being widely used in variety communication and storage systems. In this paper we present a synthesis of the new algorithms for RS, BCH and LDPC codes that have been recently proposed in this field. we also give a performance study of these algorithms, the number of the minimized logic gates and iterations will be detailed by using The bit error rate (BER) and the FPGA card Xilinx Spartan 3E-500 FG 320 FPGA (xc3s500e-5fg320).


Error correcting codes, FPGA implementation, Hardware Description Language (VHDL), FPGA Device Utilization Summary, Bit Error Rate, Minimization Rate