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Title |
Migration from Verilog based Test Flow to UVM Environment of USB -PHY |
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Author |
Shailesh kumar, Tarun K. Gupta, O.P Meena and Ajay kumar Dadoria |
| Citation |
Vol. 26 No. 3 pp. 140-144 |
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Abstract |
Increase in integration of various components in single system on chip, the verification complexity for such designs become the bottleneck now a day. In the continuous pursuit of increasing the effectiveness of verification for such blocks, UVM based verification is a step ahead of the traditional directed testbench functional verification techniques. To enable faster simulations and stay time to market, we must have flexibility to reuse our environment. UVM provides scenario for CDV, which adds self-checking testbench, faster simulations, coverage matrices, and automated test generation. We propose UVM-based environment for USB-PHY (Transceiver). We have used different UVM components in aspect to make it more flexible and structural. Through constrained random stimuli we reduce time and effort for creating hundreds of tests. We have defined assertions and covergroups derived from functional specification to ensure design quality and reduce time spent on verify the designs. |
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Keywords |
UVM, SystemVerilog, Assertion and functional coverage |
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