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Title |
Analysis of H-Parallel Prefix Circuits with Dense Faulty Nodes |
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Author |
Hatem M. El-Boghdadi |
| Citation |
Vol. 25 No. 12 pp. 1-6 |
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Abstract |
Parallel prefix circuits compute the prefix operation over a given input and are widely used in hardware systems. They play an important role in applications such as cryptography and high-performance adders, and any hardware design that incorporates adders can benefit from efficient prefix computation. Existing prefix circuits vary in performance, cost, and size, and most rely on operation nodes with fan-in and fan-out of two. One way to classify these circuits is by their width: those whose width matches the input size, and those whose width is smaller. In this paper, we focus on the first category. A well-known example of this type is the L-circuit, which performs well when the circuit width matches the input size. We analyze the behavior of the L-circuit in the presence of faulty nodes, estimating both the time delay and the number of idle nodes resulting from a fault at a given location. Based on this analysis, we propose several new designs that provide improved resilience to node failures. |
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Keywords |
parallel prefix circuits, prefix computation, faulty elements. |
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