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Abstract
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Existence of limited space in the core of CICQ switches makes these switches unable to support large buffers in switch Crosspoints, proportional to increasing of RTT delay. This factor leads to reduction of output throughput of today multi-cabinet CICQ switches with lengthy RTT delays. In order to support the increasing of RTT delay, despite limitation in size of Crosspoint buffers, a new structure namely CICQ-VCQ is at the center of attention. Although its core is considerably smaller than that of CICQ switches, offers much better output throughput. However, this switch encounters two important problems to support multiple priority levels. These are HOL Blocking and Buffer Hogging which extends the delay of sending high priority packets, and therefore reduces the quality of presenting services by these switches. In this paper, to solve these problems, the input scheduler of CICQ switch is implemented by combining two algorithms, namely Push-Out and Wait-to-Drain and the resultant switch is called PW-CICQ-VCQ. The delay of sending packets from this switch was compared with CICQ-VCQ switch, by means of simulation. It was seen that the delay of sending high priority packets in the new switch structure has reduced about 10% comparing with the old one.
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