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Title |
Embedded Static RAM Redundancy Approach using Memory Built-In-Self-Repair by MBIST Algorithm |
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Author |
Rakesh Manukonda, Suresh Nakkala |
| Citation |
Vol. 15 No. 2 pp. 80-85 |
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Abstract |
This paper proposes Memory Built in Self Repair (MBISR) approach which consists of a Built-In Self-Test (BIST) module, a Built-In Address-Analysis (BIAA) module and a Multiplexer (MUX) module. On average embedded RAMs occupy 90% area in system-on-chip (SOC), so embedded memory test design has become an essential part of the SOC development. Built-In Self-Repair (BISR) with Redundancy is an effective yield-enhancement blueprint for embedded memories. The entire design consists of a BIST (Built in self-test) which uses MARCH C- algorithm for test pattern generation (TPG), an SRAM of 6 bit address and 4 bit data that operates in 4 modes as circuit under test (CUT), a Built in Address analyzer (BIAA) for storing faulty locations of SRAM and to repair those faulty locations and a MUX module to select test data and external data. The combination of BIST, MUX and BIAA together is called as BISR (Built in Self repair) System in the design. A practical 4K × 32 SRAM IP with BISR circuitry is designed and implemented based on a 55nm CMOS process. Experimental results gives that the BISR occupies 20% area on SoC and it works up to 150MHz range. This paper is implemented using Verilog HDL. Simulation and Synthesis is done using Xilinx ISE 14.2 Tools |
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Keywords |
Built-In-Self-Repair (BISR) Built-In Address-Analysis Built-In-Self-Test Embedded SRAM Multiplexer MUX |
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