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Title |
FPGA Implementation of Network Coding Decoder |
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Author |
Taeyoon Yoon, Joonseok Park |
| Citation |
Vol. 10 No. 12 pp. 34-39 |
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Abstract |
Network Coding enhances performance of multi-cast network system, e.g., P2P(Peer-to-Peer) system. The Receivers in the network that use network coding technique have to decode the received messages which are encoded by intermediate nodes as well as sender node. Hence, decoding operations of network coding system are more complex than those of normal network system; therefore, performance of decoding operations has a significant influence on performance of the entire network system. In this paper, we address the issues regarding implementation of FPGA-based acceleration engines of Gaussian eliminations on finite Galois field. We compare the decoding performance on FPGAs with SW based implementations on P-4 processor and ARM embedded processor. The result shows that FPGA implementation outperforms contemporary widespread P-4 processor and ARM processors by 20 and 140 times, respectively. Utilizing the technique introduced in this paper, an efficient network coding system could be realized with a low level of computing resources. |
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Keywords |
Network Coding, CodeCast, FPGA, Gaussian elimination |
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