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Title |
Quaternary Sequential Circuits |
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Author |
Vasundara Patel K S, K S Gurumurthy |
| Citation |
Vol. 10 No. 7 pp. 110-117 |
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Abstract |
Application of multiple-valued logic(MVL) in the design of digital devices opens additional opportunities. D flip-flop is a basic sequential circuit in any logic. A 4-bit counter using Multiple-valued D flip-flops is presented in this paper. D flip-flop is built by 3 input NMIN gates and has both preset and clear inputs. Quaternary multiplexer and D flip-flops are used to design the quaternary counter. The circuits being studied are optimized for power and delay at 0.18-?m CMOS process technology. The new D flip-flop designed here shows 64.33 percent improvement in dynamic power dissipation when compared to DLC based flip-flop and Q-IDEN D flip-flop. The proposed Counter circuit also exhibits less dynamic power dissipation. |
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Keywords |
Multi-valued logic, Quaternary logic, multiple-valued sequential circuits, MVL counter |
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