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Title |
Design and FPGA Implementation of Fast Variable Length Coder for a Video Encoder |
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Author |
N. Venugopal, S. Ramachandran |
| Citation |
Vol. 9 No. 7 pp. 178-184 |
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Abstract |
This paper proposes a novel implementation of one of the core processors of a video encoder, the variable length coder using single FPGA. The processor is implemented on a Xilinx Virtex ? II Pro XUPVP30 FPGA. The gate count of the implementation is approximately 690,000 including an output FIFO of size 128 Kb. It can process 1600x1200 pixels color motion pictures in 4:2:0 format at over 30 frames per second as per MPEG-2 standard. The compression effected is about 38 and the reconstructed picture is of good quality with a PSNR values of 33 dB or more. |
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Keywords |
DCTQ, Encoder, RLE, FIFO, VLC |
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