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Title |
ASIC Implementation and Analysis of Extrinsic EHW Based Power and Area Optimised 8-Bit Asynchronous Parallel MAC |
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Author |
D.Dhanasekaran, K.Boopathy Bagan |
| Citation |
Vol. 9 No. 1 pp. 266-28 |
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Abstract |
In computing, especially in digital signal processing, multiply-accumulate is a common operation that computes the product of two numbers and adds that product to an accumulator. The VERILOG code for MAC operation is simulated and synthesized in Vendors tool like XILINX ISE and ALTERA QUARTUS II with different devices. Once the coding is error free the schematic for MAC unit will be generated and the bit stream to used to download is used as reference to get the approximately the same circuit by the application of extrinsic EHW using evolutionary algorithlm. This schematic obtained by EHW is realized as ASIC using Microwind to get the layout determining the area and power requirement. Depending on the different reports obtained, the optimized device which requires minimum area and less power consumption is identified.This can be applied to any devices like FPGA or CPLD of any vendor. Evolvable hardware (EHW) has attracted increasing attention since the early 1990’s with the advent of easily reconfigurable hardware, such as field programmable gate arrays(FPGA’s). It promises to provide an entirely new approach to complex electronic circuit design and new adaptive hardware. EHW has been demonstrated to be able to perform a wide range of tasks from pattern recognition to adaptive control. However, there are still many fundamental issues in EHW that remain open.In this paper it was more concentrated on the ASIC part rather than EHW because EXTINSIC EHW was used. |
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Keywords |
ASIC, EHW, Asynchronous Parallel MAC |
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