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Title |
An Efficient Hardware Architecture for H.264 Transform and Quantization Algorithms |
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Author |
Logashanmugam.E, Ramachandran.R |
| Citation |
Vol. 8 No. 6 pp. 167-173 |
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Abstract |
In this paper, we present a high performance, low cost and low power hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The proposed hardware implementation is based on a reconfigurable datapath with only one multiplier. This hardware is designed to be used as part of a complete low power video coding system for portable applications. The proposed hardware architecture is implemented using hardware description language (VHDL). The code is synthesized using Xilinx tool and downloaded into Xilinx FPGA to verify the functionality. The maximum frequency of operation of architecture is about 120 MHz. The FPGA implementation can code 39 VGA frames (640x480) per second. |
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Keywords |
H.264, Video Compression, Reconfigurable Data path, ASIC, CABAC |
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