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Title |
Integrated Operation of Image Capturing and Processing in FPGA |
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Author |
Chi-Jeng Chang, Pei-Yung Hsiao, Zen-Yi Huang |
| Citation |
Vol. 6 No. 1 pp. 173~180 |
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Abstract |
This paper presents a Field Programmable Gate Array (FPGA) integrated architecture to perform a pipelined operations of image capturing, convolution and sorting, which were usually operated in series. FPGA receives pixels from image sensor in series, when they are able to be filled in a first n×n window. A convolution with selected coefficients of n×n matrix can be started to obtain a target image pixel. After the target image pixels are filled in another n×n window again. Maheshwari sorting is performed and three values (max, mid, min) are obtained simultaneously, ready for next processing. Convolution and sorting help further filter image noises, such as dark current noise and Fixed Pattern Noise (FPN) in CMOS image sensor. This is one of the main reasons that make this integrated image processing device in FPGA demonstrate a high image qualities. A faster capturing speed is also gained due to using hardware-oriented FPGA instead of ordinary software programmed 8051 series microprocessors. This integrated processing device might relieve the microcontrollers of extensive software image computing if applied in a embedded system. |
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Keywords |
CMOS image sensor, Digital image processing, FPGA, image capturing |
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