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Title
System-on-Chip Test-time and Scan-power Minimization Integrating Core and Interconnect Testing
Author
Gautam Das, Santanu Chattopadhyay, Haripada Bhaumik
Vol. 9 No. 3 pp. 201-209
Keywords
SoC testing, Core, Interconnect test, Scan-power, Power optimization
Routing in Dynamic Network using Ants and Genetic Algorithm
Cauvery N K, K V Viswanatha
Vol. 9 No. 3 pp. 194-200
Routing, ant algorithm, genetic algorithm, crossover, mutation. Each of this is addressed in the following section
An Effective Scheme for Generating Irrevocable Cryptographic Key from Cancelable Fingerprint Templates
N. Lalithamani, K.P. Soman
Vol. 9 No. 3 pp. 183-193
Biometrics, Cancelable Biometrics, Cryptography, Biometric cryptosystems, Key generation, Irrevocable Key, Fingerprint, Minutiae Points
A Service-Oriented Component-Based Middleware Architecture for Wireless Sensor Networks
Kavi Kumar Khedo, R.K. Subramanian
Vol. 9 No. 3 pp. 174-182
Sensor networks, Middleware, Service-oriented approach, Communication model, Cluster-based routing