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Title
Test Design and Optimization for Multiple Core Systems-On-a-Chip using Genetic Algorithm
Author
SAKTHIVEL, NARAYANASAMY
Vol. 6 No. 10 pp. 121-129
Keywords
Integrated Circuit, Genetic Algorithm, System-on-Chip, Pre-Designed Core, Test Vector, Test Access Mechanism, Application Specific Integrated Circuit, Benchmark Circuit
Optimal Recovery Schemes in Distributed Computing
R. Delhi Babu, P. Sakthivel
Vol. 9 No. 7 pp. 225-230
Fault tolerance, High performance computing, Cluster technique, Recovery schemes, Sloane sequence
Improving the Performance of a Scalable Encryption Algorithm (SEA) using FPGA
Praveen Kumar. B, P. Ezhumalai, P. Ramesh, S. Sankara Gomathi, P. Sakthivel
Vol. 10 No. 2 pp. 1-5
Computer security, DES - Data Encryption Standard, VHDL ? Hardware Description Language, FPGA ? Field Programmable Gate Array
Design of Optimized Fuzzy Logic Controller for Area Minimisation and its FPGA Implementation
G.Sakthivel, T.S.Anandhi, S.P.Natarajan
Vol. 10 No. 8 pp. 187-192
Field programmable gate array, VHDL, FLC, optimization