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Title
Test Design and Optimization for Multiple Core Systems-On-a-Chip using Genetic Algorithm
Author
SAKTHIVEL, NARAYANASAMY
Vol. 6 No. 10 pp. 121-129
Keywords
Integrated Circuit, Genetic Algorithm, System-on-Chip, Pre-Designed Core, Test Vector, Test Access Mechanism, Application Specific Integrated Circuit, Benchmark Circuit
Object-Oriented System-on-Network-on-Chip Template and Implementation
S.ANANDARAJ
Vol. 14 No. 6 pp. 24-30
network-on-chip, system-on-chip, system-on-network-on-chip
A New Irregular Fault-Tolerant Routing Algorithm in Network-on-Chip
Davood Abednezhad, Seyed Enayatallah Alavi
Vol. 17 No. 4 pp. 166-171
3D NoC, System-on-Chip, irregular, Fault tolerant routing, Congestion, Enhanced odd-even