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Title
A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box
Author
Muhammad H. Rais, Syed M. Qasim
Vol. 9 No. 9 pp. 305-309
Keywords
Advanced Encryption Standard (AES), Very High Speed Integrated Circuit Hardware Description Language (VHDL), Field Programmable Gate Array (FPGA), Virtex-5