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Results for VHDL Simulation ; Total 1

Title

Performance Analysis of a 64-bit signed Multiplier with a Carry Select Adder Using VHDL

Author

Deepthi, Rani, Manasa
Citation

Vol. 15  No. 11  pp. 91-94

Keywords

Signed Multiplier, Carry-Look-Ahead Adder, Carry Select Adder, Wallace tree, VHDL Simulation & Synthesis.

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