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Title
Test Design and Optimization for Multiple Core Systems-On-a-Chip using Genetic Algorithm
Author
SAKTHIVEL, NARAYANASAMY
Vol. 6 No. 10 pp. 121-129
Keywords
Integrated Circuit, Genetic Algorithm, System-on-Chip, Pre-Designed Core, Test Vector, Test Access Mechanism, Application Specific Integrated Circuit, Benchmark Circuit
A Probabilistic Behavioral Model for Selfish Neighbors in a Wireless Ad Hoc Network
K. Komathy, P. Narayanasamy
Vol. 7 No. 7 pp. 77-83
Co-operation, Selfishness, Reputation, Trust, Ad Hoc routing, Markov Chain
A Novel Mobility Based Bandwidth Reduction Algorithm in Cellular Mobile Networks
Karthikeyan N.K., Narayanasamy P.
Vol. 8 No. 5 pp. 62-69
Cellular networks, linear programming, bandwidth, mobility call admission control