Title	A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box
Author	Muhammad H. Rais, Syed M. Qasim
Citation	Vol. 9  No. 9  pp. 305-309
Keywords	Advanced Encryption Standard (AES), Very High Speed Integrated Circuit Hardware Description Language (VHDL), Field Programmable Gate Array (FPGA), Virtex-5

Title	Performance study and synthesis of new Error Correcting Codes RS, BCH and LDPC Using the Bit Error Rate (BER) and Field-Programmable Gate Array (FPGA)
Author	El habti El idrissi Anas, El gouri Rachid, Ahmed Lichioui, Hlou Laamari
Citation	Vol. 16  No. 5  pp. 21-28
Keywords	Error correcting codes, FPGA implementation, Hardware Description Language (VHDL), FPGA Device Utilization Summary, Bit Error Rate, Minimization Rate