Title	A Formal Verification Case Study for IEEE-P.896 Bus Arbiter by using A Model Checking Tool
Author	Katsumi Wasaki
Citation	Vol. 7  No. 3  pp. 184-192
Keywords	Formal Verification, Model Checking, Temporal Logic, Bus Arbiter, Hardware Description Languages

Title	Design approach for VHDL and FPGA Implementation of Automotive Black Box using CAN Protocol
Author	Milind Khanapurkar, Preeti. Bajaj, Sandesh Dahake, Hemant Wandhare
Citation	Vol. 8  No. 9  pp. 214-218
Keywords	CAN: Controller Area Network, FPGA: Field Programmable Gate Array, VHDL: Very High Speed Hardware Description Language, ADC: Analogue to Digital Converter, DIP: Dual In line Package.

Title	A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box
Author	Muhammad H. Rais, Syed M. Qasim
Citation	Vol. 9  No. 9  pp. 305-309
Keywords	Advanced Encryption Standard (AES), Very High Speed Integrated Circuit Hardware Description Language (VHDL), Field Programmable Gate Array (FPGA), Virtex-5

Title	Improving the Performance of a Scalable Encryption Algorithm (SEA) using FPGA
Author	Praveen Kumar. B, P. Ezhumalai, P. Ramesh, S. Sankara Gomathi, P. Sakthivel
Citation	Vol. 10  No. 2  pp. 1-5
Keywords	Computer security, DES - Data Encryption Standard, VHDL ? Hardware Description Language, FPGA ? Field Programmable Gate Array