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Title
FPGA Based Hardware Implementation of Image Filter With Dynamic Reconfiguration Architecture
Author
B. Rajan, S.Ravi
Vol. 6 No. 12 pp. 121-127
Keywords
Reconfigurable computing, FPGA implementation, Image processing.
An Efficient VLSI Architecture and FPGA Implementation of High-Speed and Low Power 2-D DWT for (9, 7) Wavelet Filter
A. Mansouri, A. Ahaitouf, F. Abdi.
Vol. 9 No. 3 pp. 50-60
JPEG2000, 2D-DWT, VLSI architecture, FPGA implementation
FPGA Implementation and Mask Level CMOS Layout Design of Redundant Binary Signed Digit Comparator
Krishna Raj, Brijesh Kumar, Poornima Mittal
Vol. 9 No. 9 pp. 107-115
Redundant Binary Signed Digit (RBSD), comparator, VHDL, FPGA implementation, CMOS etc
Performance study and synthesis of new Error Correcting Codes RS, BCH and LDPC Using the Bit Error Rate (BER) and Field-Programmable Gate Array (FPGA)
El habti El idrissi Anas, El gouri Rachid, Ahmed Lichioui, Hlou Laamari
Vol. 16 No. 5 pp. 21-28
Error correcting codes, FPGA implementation, Hardware Description Language (VHDL), FPGA Device Utilization Summary, Bit Error Rate, Minimization Rate