Title	Performance study and synthesis of new Error Correcting Codes RS, BCH and LDPC Using the Bit Error Rate (BER) and Field-Programmable Gate Array (FPGA)
Author	El habti El idrissi Anas, El gouri Rachid, Ahmed Lichioui, Hlou Laamari
Citation	Vol. 16  No. 5  pp. 21-28
Keywords	Error correcting codes, FPGA implementation, Hardware Description Language (VHDL), FPGA Device Utilization Summary, Bit Error Rate, Minimization Rate