Title	A Formal Verification Case Study for IEEE-P.896 Bus Arbiter by using A Model Checking Tool
Author	Katsumi Wasaki
Citation	Vol. 7  No. 3  pp. 184-192
Keywords	Formal Verification, Model Checking, Temporal Logic, Bus Arbiter, Hardware Description Languages

Title	Design and Performance analysis of efficient bus arbitration schemes for on-chip shared bus Multi-processor SoC
Author	Neeta Doifode, Dinesh Padole, P.R. Bajaj
Citation	Vol. 8  No. 9  pp. 250-255
Keywords	System-on-Chip (SoC), Bus Arbiter, VHDL, Multiprocessor